3D packaging is a type of MEMS packaging that involves two or more components stacked vertically in a package in order to achieve a higher level of integration while using a smaller footprint. The integrated components may be either stacked packages or stacked chips. In the later case, the chips are either wire-bonded along their edges or interconnected by way of Through-Silicon Via (TSV) technology.
Accelerated Lifetime Test (ALT)
A methodology used to test a product under more severe conditions than the specified normal operating condition in a relatively short period of time in order to identify the failures and the associated accelerating models. Once the lifetime limiting failure mechanism is confirmed, and its accelerating model is understood, the product lifetime in normal operating condition can be estimated through the ALT data.
A process to alter wafer properties by heating. An example is a bond anneal where wafers are heated in a furnace to form strong bonds between the handle and device wafers in the formation of SOI.
A technique of hermetically joining glass to silicon by applying heat and electric field. The silicon and glass wafers are heated to a temperature, typically in the range of 200-500 deg. C, and are applied with a high voltage, typically in the range of 500 to 1,500 V, across them. This causes the mobile alkali cations in the glass to migrate from the interface resulting in a depletion layer with high electric field strength. The resulting electrostatic attraction joins the silicon and glass wafers together. Anodic wafer bonding is often used to fabricate MEMS pressure sensors, inertia sensors, RF and microfluidic devices.
In accelerated lifetime modeling, when the stress parameter is the temperature the acceleration factor may follow an Arrhenius equation where the acceleration factor is proportional to exp(-Ea/kT) with Ea being the activation energy, k the Boltzmann constant and T the temperature.
Assembly Test Chip
A chip designed to evaluate the reliability and effect of assembly materials and processes, usually by electrical measurements made on terminals connected to the chip within the packages that are tested. The test chip may contain a variety of sensors to evaluate thermomechanical stresses, moisture, and other associated degradations.
The back-end of semiconductor processing commonly refers to the operations that take place after the processes that build multiple microdevices on a silicon wafer (front-end processing). Back-end processing typically involves the separation of the silicon wafer into individual die (singulation), followed by the addition of electrical wiring, die packaging and final testing. In some cases, wafer bonding may be required before singulation.
Ball Grid Array (BGA)
A surface mount microelectronic package that uses an array of solder balls to provide electrical interconnect and physical mount to the next level of package such as a printed circuit board.
A high-level representation of an electronic or electromechanical design that describes the behavior of various components in the system, usually without regard to the underlying technology used to implement the design.
A miniature silicon, glass or plastic piece consisting of a large number of microstructures containing special probes of biologically active molecules to be used as an analytical and diagnostic tool. For example, the biochip make it possible to identify very large numbers of genes or proteins (protein chip) in relative short time.
Biological or Biomedical Micro Electro Mechanical Systems are microsystems with applications for biological, biomedical and analytical instrumentation fields. Examples of BioMEMS include devices and microsystems for drug delivery, DNA/protein analysis, molecular manipulation/assembly, microfluidics as well as biosensors and micro total analysis systems.
A wireless technology that specifies how mobile devices, peripherals and computers that are in close proximity to communicate with each other. The technology enables data connections between electronic devices in the 2.4 GHz range. Bluetooth would replace cable or infrared connections for such devices. MEMS displays, microphones and RF devices are emerging for Bluetooth-based applications.
Bluetooth is a registered trademark of the Bluetooth SIG Corporation.
Bonded Silicon-on-Insulator (SOI) Wafer
SOI wafer formed by bonding a device quality silicon wafer to a handle silicon wafer. Either or both of the two silicon wafers may have an oxide layer to form the buried oxide layer, which is the oxide layer between the handle and device wafers.
The process of joining, two or more entities, components or wafers to each other by means of various chemical and physical effects -- such as adhesive, anodic, eutectic and thermal compression bondings.
An subtractive micro-fabrication process where MEMS devices are built by etching into the interior of the substrate, such as a piece of a silicon or a glass wafer, to form the micro electro mechanical structures. The etching techniques can be either a wet etching in a solution or dry etching in a plasma system.
A raised conductive feature on a die or wafer that facilitates inner-lead bonding
Buried oxide (BOX)
Buried oxide layer- the insulating layer between the handle and device wafers.
The process of electrically stressing a device, usually at an elevated temperature and voltage environment, for an adequate period of time in order to force component infant mortality failures or other latent defects before the unit is delivered to a customer.
A wafer that is bonded to a device wafer intended to provide encapsulation to the devices.
The process of bonding a cap to a MEMS device. Capping may be done either at wafer level or at die level.
An inorganic, nonmetallic material, such as alumina and beryllia, whose final characteristics are produced by subjection to high temperatures. Ceramic materials are commonly used as substrates for packaging microelectronic devices.
Ceramic Ball Grid Array (CBGA)
A ceramic surface-mount package that uses an array of solder balls to provide electrical interconnect and physical mount to the next level of package such as a printed circuit board.
Chemical Mechanical Planarization (CMP)
The use of an abrasive slurry to polish a wafer's surface to eliminate topological layer effects in the manufacturing of semiconductors. In the process the chemicals in the slurry reacts with the material to be removed to assist the mechanical polishing.
Chemical Vapor Deposition (CVD)
A film deposition process onto heated silicon wafers based on a chemical vapor reaction in a vacuum chamber. Commonly deposited film materials by CVD include silicon nitride, silicon dioxide and poly-silicon.
An uncased and normally leadless form of a microelectronic component that is either passive or active, discrete or integrated. It is the square or rectangular portion of a wafer sectioned from the wafer when the wafer processing is completed. Also referred to as a die.
Chip Scale Package (CSP)
According to IPC/JDEC J-STD-012 standard, CSP is a single-die, direct surface mountable package with an area of no more than 1.2 X the original die area. CSPs are constructed from individual die with lead frame or substrates and are also fabricated at the wafer level. CSPs have the advantage of small size, low mass, reduced electrical parasitics and they can be fully tested.
Coefficient of Thermal Expansion (CTE)
A thermal property of a material defined as the ratio of the change in length to the original length per degree C of temperature change. CTE is also referred to as Temperature Coefficient of Expansion (TCE)
Excess electrical resistance in series with the bulk conductor resistance of two contacting electrical conductors arising from the nature of contact geometry and properties of the contact surfaces.
Non-recoverable deformation proceeding at relative low strain rates, usually associated with high temperature to allow sufficient rates of diffusion.
The undesirable interference caused by the coupling of energy between signal paths.
For a polymeric material, such as a die-bonding adhesive for pressure sensor chip, the curing cycle is the combination of total time-temperature profile in the heat treatment to achieve the desired results of bonding.
Deep Reactive Ion Etching (DRIE)
A “dry” vertical etching process used to create deep, steep-sided structures, cavities and trenches in silicon wafers. The process involves the alternating modes of ion etching and passivation-layer deposition in order to create a near vertical etching profile. It is commonly used to form high-aspect-ratio features in MEMS, trenches for high-density capacitors for DRAM, and through-silicon via (TSV) technology.
Design For Manufacturability (DFM)
A product design approach that includes a set of techniques conducted at the early stage of the development cycle to make the product more manufacturable, i.e. to achieve the optimization for the cost, quality, reliability and manufacturing capabilities of a product.
Design for Testability (DFT)
A product design approach, which includes a set of techniques to incorporate testable features and/or circuitry to the design in order to make it easier to develop and to aid in the testing of the fabricated product.
Single crystal silicon layer of silicon on insulator (SOI) wafers on which devices are fabricated.
An uncased and normally leadless form of a microelectronic component that is either passive or active, discrete or integrated. It is a square or rectangular portion of a wafer sectioned from the wafer when the wafer processing is completed. Also referred to as a chip.
The mechanical bonding of a die to a base material usually by solder, epoxy, silicone rubber, gold-silicon eutectic or other bonding agent. Also referred to as Die Bonding.
The mechanical attachment of a die to a base material usually by solder, epoxy, silicone rubber, gold-silicon eutectic or other bonding agent. Also referred to as Die Attachment.
A die bonder, in contrast to a wafer bonder, handles electronic components that have already been separated from the wafer. The component is then either bonded to another wafer or to another diced component before final packaging.
Dual-in-Line Package (DIP)
A type of package with two rows of leads extending at right angles from the base and having standard spacing between leads and between rows of leads. DIP is a through-hole mounting package. DIPs can be made of ceramic and plastic, referring to as CERDIP and PDIP respectively.
Impurity doping is the introduction of controlled amounts of impurity dopants into semiconductors either by diffusion or ion implantation. For silicon, boron and phosphorus are the most common dopants for p- and n-type materials, respectively.
The deposition of an adherent metallic coating on to a conductive object placed into an electrolytic bath composed of a solution of salt of the metal to be plated.
Sealing up or covering a circuit or electromechanical element for mechanical and environmental protection.
Epitaxial (epi) Wafer
A wafer with a single-crystal semiconductor layer grown upon a single-crystal substrate having the same crystallographic characteristics as the substrate material.
Process by which material is removed from the wafer in a pattern already transferred lithographically. This may be achieved chemically in a process referred to as “wet” etching using chemical solutions, or with a “dry” etch in a plasma, where a controlled gas flow is ionized and reacts with surface material on the wafer with a physical bombardment of particles.
The melting point of a mixture of two or more solids, such as an alloy, depends on the relative proportions of its constituents. An eutectic or eutectic mixture is a mixture whose melting point is lower than that of any other alloy composed of the same constituents in different proportions.
This temperature is referred to as the eutectic temperature of the alloy.
A technique of hermetically joining work pieces, such as silicon wafers, together by using eutectic material such as Si-Au alloy. Eutectic wafer bonding requires precise application of force and temperature to control the reflow of the eutectic material and is being used in hermetic packaging, 3D integration, compound semiconductor and MEMS fabrication.
A physical, chemical or other processes that leads to failure. Some examples of failure mechanisms in MEMS include: stiction, creep, fatigue, wear, dielectric charging and breakdown.
A failure mode is the manner whereby a failure is observed. Generally, it describes the way in which the failure happens and its impact on device or system operation.
Failure Mode and Effect Analysis (FMEA)
A systematic method for evaluating potential product or process failure modes and their impact on the product or process. FMEA is normal done on a form which facilitates the prioritization and management of remedial actions to reduce the occurrence of failure modes or minimize their effects.
A company that does not manufacture its own integrated circuits or MEMS devices but outsources its manufacturing to an outside foundry.
Used to describe the failure of any structure caused by repeated application of stress over a period of time.
Finite Element Analysis (FEA)
A computational intensive numerical modeling tool in which the body is discretized into small regular shaped elements. Also referred to as Finite Element Modeling.
A leadless, monolithic structure containing microelectronic elements that is designed to electrically and mechanically interconnect to a base material through the use of conductive bumps located on its face.
A micro-fabrication business operation that provides services for prototyping and volume production of integrated circuits and/or MEMS microchips. Foundry services typically offer a set of standard fabrication process, however, some may offer specialized and/or customized services including the design and simulation of MEMS devices.
Convetionally, the front-end of semiconductor processing refers to the operation of forming repeated microdevices built on the silicon wafer. Front-end processes typically involve repeated steps of photolithography, oxidation, ion implantation, diffusion, film deposition, and etching. The outcome is a silicon wafer that contains multiple units microdevices prior to separating into chips.
Getters are materials which, when properly activated, can remove traces of gas in a vacuum package by reacting with gas molecules.
2-D mask layout binary file format used to generate masks for photolithography processes during the fabrication of microelectronic circuits and MEMS devices.
Glass composition ground into a powder form. It melts upon firing to yield adhesion of other materials. Glass frit is a common material used as an intermediate layer for wafer bonding.
Glass Transition Temperature
The glass transition temperature, Tg, is a transition temperature that below which an amorphous solid (such as glass or a polymer) becomes relatively hard and brittle; whereas above which the object becomes viscous or rubbery.
Refers to a condition where a unit is sealed and gas tight. A conventional test for hermiticity is to fill the unit with a test gas, such as helium, and measure the leak rates when placed in vacuum. For MEMS vacuum packages with a very small volume, on-chip sensors such as a resonator have been used to evaluate the hermitic encapsulation by monitoring the quality factor of the resonator.
A sensor possessing advanced features such as self-calibrating, self-diagnostics, and the ability to compensate for variations in ambient conditions. The key factor of an intelligent sensor is to have adequate information from which the sensor can assure validity of the measurement and the ability to communicate with other intelligent devices.
Intellectual Property (IP)
IP has to do with property that is produced by effort of the mind. Industrial IPs are those created and used for industrial or commercial purposes including inventions (patents), copy rights, trademarks, trade secrets and others. For the MEMS industry, IP may include copyrights of masks, patents for device or system design and methods of fabrication, as well as trade secrets such as process recipes.
An intermediate layer in packaging, used for purposes such as fanning out or matching electrical interconnects from one device to another, or relieving any potential stress issues.
Known Good Die (KGD)
An unpackaged die (or chip) that has been tested and proven to meet required functional and performance specifications.
Process used for performing an angular etch where by a heated Potassium Hydroxide (KOH) solutions is used for preferential crystallographic etching of Silicon (Si). The etch rate depends on the doping and crystallographic orientation of the Si and the type (concentration) of KOH used.
A miniature analytical system, that contains microfluidic channels to allow minute liquid of gas to be separated and analyzed by integrated microdevices including pumps, valves, microfluidic controllers, and detectors. LOCs are typically made of silicon, glass or plastic and are the size of a credit card. These miniature labs can perform tasks such as drug discovery, genetic testing and the separation of cells.
Method used to create three-dimensional structures in materials (such as silicon, glass, plastics, etc.) by focusing a highly collimated, monochromatic, coherent light beam at the work-piece
LIGA is the German acronym for Lithographie, Galvanofomung and Abformung, meaning Lithography, Electroforming and Molding. It is a micromachining technique used to create a very tall, straight-walled (high-aspect ratio) photoresist microstructure followed by electroplating to form a metal microstructure. The metal microstructure may be may be the final product or serve as a mold insert for precision plastic injection molding.
The degree to which the calibration curve of a device conforms to a straight line.
Pattern on glass, like a photographic negative, for producing integrated-circuit elements on semiconductor wafer.
Mean Time To Failure (MTTF)
MTTF is a characterization of reliability for non-repairable systems. It is the mean time expected until the first failure of a part of the system. MTTF is a statistical value and is supposed to be the mean over a long period of time and large number of units.
MEMS Device Taxonomy
An aid in the classification of MEMS device with respect to their reliability. The taxonomy consists of four classes of MEMS devices:
• Class I: Parts may flex but no moving parts for excited displacement nor vibration (e.g. pressure sensors, Ink jet print head) ;
• Class II: Moving parts with no contact (e.g. comb-drive accelerometers, resonators);
• Class III: Moving parts with contact (e.g. switches, fluidic valves)
• Class IV: Moving parts with rubbing and/or contact (e.g. gears, rotary hubs.
Micro Electro Mechanical System (MEMS)
An enabling microfabrication technology that use manufacturing processes similar to that of semiconductors and integrated circuits to create discrete or integrated microdevices such as mechanical structures, microsensors, microactuators, and circuitry on a substrate material including silicon, glass or ceramic. MEMS products find wide applications in instrumentation, industrial automation, automotive, telecommunications, optoelectronics, information technology and consumer electronics. In referring to this technology, MEMS is the term commonly used in North America whereas Microsystem Technology (MST) and Micromachines are commonly used in Europe and Japan respectively.
Packaging of MEMS needs to meet the basic functional requirements, including electrical signal/power interconnections, heat dissipation, mechanical integrity, and environmental protection. In addition, it also has to provide an interface with the environment in order to perform sensing or actuation.
Mirrors of micro feature size fabricated on a chip. Micromirrors are commonly actuated by electrostatic, thermal, or magnetic means steer and/or scan a light beam with applications for displays, scanners, optical switches and other optoelectronics components.
Microsystem Technology (MST)
An enabling microfabrication technology that uses manufacturing processes similar to that of semiconductors and integrated circuits to create discrete or integrated microdevices and systems. MST products find wide applications in instrumentation, industrial automation, automotive, telecommunications, optoelectronics, information technology and consumer electronics. In referring to this technology, MST is the term commonly used in Europe whereas MEMS and Micromachine are commonly used in North America and Japan respectively.
Microfluidic systems comprised of nozzles, pumps, reservoirs, mixers, valves, etc., can be used for a variety of applications including drug dispensing, ink-jet printing and general transport of liquid, gases and their mixtures
Structures and machines with micron feature sizes. It also refers to a microfabrication technology that uses manufacturing processes similar to that of semiconductors and integrated circuits to create discrete or integrated microdevices such as mechanical structures, microsensors, microactuators, and circuitry on a substrate material including silicon, glass or ceramic. MST products find wide applications in instrumentation, industrial automation, automotive, telecommunications, optoelectronics, information technology and consumer electronics. In referring to this technology, the term Micromachine is commonly used in Japan whereas MEMS and Microsystem Technology (MST) are commonly used in North America and Europe respectively.
Micro-Optical-ElectroMechanical Systems (MOEMS)
MOEMs generally refer to micofabricated optic components or optoelectronics devices and systems including waveguides, diffraction gratings, moving mirrors and other products that alter or modulate the path of a light beam, or spectrally modify the light beam. It is also known as optical MEMS.
A chip carrier on which the chip terminals are fed out by various means to terminals spaced to suit the spacing and dimensions of wires on the level higher level of package such as a board.
Modulus of Elasticity
A measure of the stiffness of a material in the elastic range. It is determined from the slope of a stress-strain curve obtained during tensile tests on a sample of the material. Modulus of Elasticity is also known as Young’s Modulus.
Multichip Module (MCM)
A module of package capable of supporting several microelectronic chips in a single package. Most multichip packages are made of ceramic.
Multichip Package (MCP)
A small enclosed module with an external form factor that matches a single chip package and typically contains two to five chips. MCPs are commonly low lead count combinations of simple IC's.
The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors density on integrated circuits had doubled every 18 months since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future.
MUMPs® (Multi-User MEMS Processes)
A commercially available service that provides customers with cost-effective access to a set of multi-layer, MEMS prototyping processes with wafer costs being shared among multiple users and individual die being the final deliverable.
MUMPs is a registered trademark of MEMSCAP S.A. Corporation
Open-Cavity Package (OCP)
Packages that have been fabricated in advance with an open cavity to accept a MEMS or IC chip as a fast turn-around and cost-effective packaging solution for prototyping, sampling, and low-volume production. Open access to the chip within the package enables special inspection, testing, probing, and even repair. OCP options include QFP, BGA and other package types which match the standard packages from those families.
Process by which SiO2 is thermally grown on silicon.
The formation of an insulation layer over the surface of an microelectronic element to serve as a barrier to further oxidation or corrosion. It also protects the surface from contaminants, moisture, or particles.
Photolithography (also called optical lithography) is a process used in microfabrication to selectively remove parts of a thin film (or the bulk of a substrate). It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical (photoresist, or simply "resist") on the substrate.
The science and technology of generating, manipulating, transmitting, and detecting light. It is a field that encompasses optics, quantum optics, lasers, optoelectronics, imaging, optical information processing, materials science, and their applications.
A ferroelectric material in which an electrical potential difference is created due to mechanical deformation, or conversely, in which the application of a voltage causes dimensional changes in the material.
Diagram showing for electronic components the relations between connecting pins and internal components.
The term pinhole embraces a wide variety of oxide defects and is used in a broad sense today. Listed in this category are cracks caused by thermal contraction after oxidation or by handling, and regions of oxide with low dielectric strength caused by dust particles, inadequate masking, contamination, or poor resist adhesion.
A form of very localized corrosion wherein small pits or holes form, usually in a vertical direction.
Polycrystalline silicon used as conductor in integrated circuits, and especially FETs.
Quality Factor (Q Factor)
A figure of merit for assessing the performance or quality of a resonator, the quality factor, is a measure of energy loss or dissipation per cycle as compared to the energy stored in the fields inside the resonator. It is defined as the ratio of the reactance to the effective series resistance of a component at resonance. For example, a MEMS resonator with a high Q factor has a sharp, large magnitude, well-defined peak in the resonance curve.
Quad Flat Package (QFP)
A microelectronic package with leads extending from each of its four sides. It is used primarily for surface mounting and its variations include Low-Profile QFP (LQFP) and Thin QFP (TQFP).
Quality Function Deployment (QFD)
A structured methodology that begins in the product design process and conducted by a cross-functional team to capture and to reach consensus on appropriate technical requirements based on customer-desired expectations and definitions of quality.
Radio Frequency Identification (RFID)
A method of identifying unique items using radio waves. Typically, a reader communicates with a tag, which holds digital information in a microchip. But there are chipless forms of RFID tags that use materials to reflect back a portion of the radio waves beamed at them.
The deprocessing and analysis of a competing product in order to gain insights of its technology features as well as its comparative strengths and weaknesses.
Reactive Ion Etch. Plasma process technology for etching pre-patterned structures into substrates.
RTP (Rapid Thermal Processing)
A semiconductor manufacturing processing that uses radiant heating from halogen-quartz lamps to rapidly heat up the wafers
A temporary layer used in surface micromachining to form MEMS structures but etched at later stage of the wafer fabrication to release the MEMS structures.
Self-Assembled Monolayer (SAM)
Self-assembled monolayer is a coating commonly applied to the MEMS to reduce moisture-induced stiction of the parts.
Silicon Fusion Bonding
A process for bonding two silicon wafers using special che¬mical treatments of the bonding surfaces, often to be followed by an annealing process at high temperature.
Silicon on Insulator (SOI)
A process where a single-crystal silicon layer is created by insulating a substrate. SOI wafers may be fabricated by deposition, oxygen ion implantation or wafer bonding and grinding techniques.
Silicon on Sapphire (SOS)
A process where SOI is formed by bonding a device quality Sapphire wafer is bonded to a silicon handle wafer. Either or both of the two substrates may have an oxide layer to form the. buried oxide layer.
The electrical resistance of thin sheet of a material with uniform thickness as measured across opposite sides of a unit square pattern. It is expressed in ohms per square.
The use of a computer-aided-design tool that mimics the behavior of the actual system through a collection of sub-system models enabling designers to test, verify, and debug circuits before layout and fabrication.
Small Outline Integrated Circuit (SOIC)
A type of microelectronic package which is smaller than the normal dual-in-line package. The pins are closer together and are bent flat so that the package may be soldered to the surface of a substrate or a circuit board.
SiP refers to multiple silicon chips enclosed in a single package or module to perform essentially the functions of a system. Examples of chips integrated in the package include processors, memories, wireless communications, RF-MEMS and discrete passive components. SiPs are typically used inside a mobile phone, digital music player, etc.
In a MEMS packaging concept, the smart cap refer to the cap on a MEMS die that contains circuitry which is interconnected to the MEMS die.
A sensor in which the electronics that process the output from the sensor, and forms the modifier, are partially or fully integrated on a single chip.
A large, complex silicon integrated-circuit with high functionality and performance. Often characterized by the presence of embedded processors, memory, and a multiple number of other components.
SoP refers to the integration of a wide variety of component types (such as RF, digital, analog, optical and MEMS) in one package to achieve system-level functions. It uses thin-film component technology and is often built on a multi-layer package substrate by lateral and vertical integration to achieve a multi-function system-level package. It goes further than System-in-Package (SiP) by incorporating multi-domain components based-on materials beyond silicon. It can include systems-on-chips (SoC), SiP, multi-chip module (MCM) and 3D chip-stacking for both IC and package integration as well incorporate multi-domain devices such sensors, optoelectronics, RF and MEMS (including Bio-MEMS, microfluidics, etc) components for system-level integration.
Short for “Static Friction.” The friction that tends to prevent stationary surfaces from being set in motion. For MEMS devices, it refers to the tendency of surfaces to stick together caused by formation of weak hydrogen bonds or other physi-sorption surface bonds.
The amount of deformation of a body under load normalized by the dimensions of that body.
An element (wire or foil) that measures a strain based on electrical resistance changes of the gauge that result from a change in length or dimension strain of the wire or foil.
The force per unit area acting on a plane within a body.
An additive micro-fabrication process where MEMS devices are built by the deposition and selectively etching of thin films on a substrate. Often some of the films, referred to as sacrificial layers, are removed at the conclusion of the micro-fabrication process to release a freestanding movable MEMS structure.
Surface Mount Technology (SMT)
The technology for the assembly of hybrid circuits and printed circuit boards by soldering electronic components directly to a board substrate that uses less space than the pin-through-hole method.
Temperature Coefficient of Expansion (TCE)
A thermal property of a material defined as the ratio of the change in length to the original length per degree C of temperature change. TCE is also referred to as Coefficient of Thermal Expansion (CTE).
The process involving the use of pressure and temperature to join two materials together by interdiffusion across the boundary. For example, thermocompression is commonly used for gold wire-bonding in microelectronics assembly and wafer-to-wafer boning in MEMS using gold as an intermediate layer.
A measure of the property of a solid to conduct heat in the unit of W/mºK. For microelectronics, the higher the thermal conductivity of the substrate material, the higher the efficiency of the removal of heat is during device operation.
Through-Silicon Via (TSV)
TSV is a vertical electrical connection passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. TSV involves the processes of via formation, insulator/barrier/seed deposition, via filling, surface metal removal, wafer thinning, bonding/stacking, inspection, test, etc. One of the few TSV-based products in the market is a CMOS image sensor. Other TSV devices are demonstrated by major companies, including memory houses and package service foundries.
A process that uses ultrasonic vibration energy and pressure to join two materials.
A process of encapsulation of MEMS device in vacuum. The dealing may be achieved in wafer fabrication by a film deposition process in vacuum to seal a chamber which is created with the removal of a sacrificial layer. Alternately, the vacuum sealing of MEMS device can be done by wafer capping in vacuum.
A thin, circular piece of silicon, glass, sapphire or other substrate material onto which the integrated circuits, discrete or MEMS devices are fabricated. A wafer normally consists of an array of multiple devices which is referred to as a chip, or die, after separated from the wafer.
The wafer bonder is a processing tool to bond together two or more wafers under very precisely controlled conditon. Wafer bonder is an essential tool for MEMS fabrication and 3D semiconductor integration.
A process that bonds two or more wafers together using a wafer bonder in a controlled ambient and heating conditions with high precision of alignment and contact pressures.
The process of providing electrical connection from the die to the package by bonding metal wires, such as gold and aluminum wires, from the conductive pads on the die to the leads of the package.
The process of physically capping the MEMS device at the wafer level before singulation.
Wafer-Level Chip-Scale Package (WLCSP)
WLCSPs are chip-scale microelectronic packages that are processed at the wafer level to form a fine-pitch I/O format which can be tested and surface mounted on a printed circuit board. For example, in one approach, a dielectrically-isolated redistribution layer connected to the die pads is created on the wafer and followed by the formation of solder ball bond pads, resulting in a package very close to the size of the silicon die.
Wafer-Level Packaging (WLP)
The technology of packaging an integrated circuit or a MEMS device at wafer level as oppose to the traditional packaging of individual device after wafer dicing. WLP accomplishes device interconnection and protection at wafer level involving processes such as interconnect redistribution layer, bumping, encapsulated metal conductors or wire bonding, through-silicon-via, wafer bonding, etc. WLP for MEMS such as imaging sensors and mciromirror arrays has potential for cost reduction, size shrinkage and performance enhancement.
Process that uses x-ray radiation to expose the resist through a mask which typically consists of a membrane of a material that has low x-ray absorption, with a pattern of highly absorbing material such as gold.
A measure of manufacturing efficiency expressed as the percentage of acceptable prodcution units obtained from a specified manufacturing process. For example, die yied is the percentage of acceptable die compared to the total number of die on a processed wafer.
A measure of the stiffness of a material in the elastic range. It is determined from the slope of a stress-strain curve obtained during tensile tests on a sample of the material. Young’s modulus is also known as Modulus of Elasticity.
ZigBee is a low-data-rate, short-range wireless communication standard for home automation and data networks. ZigBee is slower than Wi-Fi and Bluetooth, but is designed for low power so that batteries can last for months and years. The typical ZigBee transmission range is roughly 50 meters, but that can vary greatly depending on environment conditions. MEMS-based acceleration and pressure sensor ICs compatible with the ZigBee protocol are developed to enable the deployment of wireless sensor networks for industrial, medical, automotive or consumer electronics applications.
ZigBee is a registered trademark of the ZigBee Alliance